It is a common occurrence in digital systems on a chip (SOC) to uniquely identify instances of digital circuits so that they can be independently addressed by the system to perform a function. The process of assigning an identifier to each addressable instance is referred to as “enumeration”.
Typically, enumeration is carried out by connecting the circuits in a serial “daisy-chain”, in which each circuit to be enumerated has an enumeration in port, an enumeration out port, and an enumeration control port. When the enumeration control is asserted, each circuit begins simultaneously counting. When a change in state is detected at the enumeration in port of a given instance, it stops counting. The value of the counter becomes the enumeration instance number. The enumeration output is simply the value received at the enumeration in port delayed by 1 clock-cycle. The limitation with this approach is that all of the circuits to be enumerated must be synchronous to each other, and the enumeration control signal must simultaneously arrive at all enumerable instances.
The enumeration implementation that has been in place for several generations has been designed around the assumption that all components of the system are synchronous. In this type of implementation, each enumerable instance contains an enumeration counter, which, upon assertion of a global ENABLE signal, all count in lock-step until each instance sees a “1” on the enumeration daisy-chain input, at which point the counter stops and holds its value.
However, in the next generation of ASIC technology, the industry will be moving to an IJTAG (IEEE P1687) interface, in which the control signals will no longer be global and synchronous. Instead, an asynchronous boundary crossing of the ENABLE signal will introduce some uncertainty of the arrival of the enable signals to each enumerable instance. If the existing logic were to be used, the uncertainty of the ENABLE signal could result in duplicate enumeration values or gaps in the enumeration numbering.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.